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PH3830L N-channel TrenchMOS logic level FET Rev. 04 -- 17 November 2009 Product data sheet 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and qualified for use in computing, communications, consumer and industrial applications only. 1.2 Features and benefits Higher operating power due to low thermal resistance Low conduction losses due to low on-state resistance Suitable for logic level gate drive sources 1.3 Applications DC-to-DC convertors Notebook computers Portable equipment Switched-mode power supplies 1.4 Quick reference data Table 1. VDS ID Ptot Quick reference Conditions Tmb = 25 C; VGS = 10 V; see Figure 1 and 3 Tmb = 25 C; see Figure 2 Min Typ Max 30 98 62.5 Unit V A W drain-source voltage Tj 25 C; Tj 150 C drain current total power dissipation gate-drain charge Symbol Parameter Dynamic characteristics QGD VGS = 5 V; ID = 20 A; VDS = 10 V; Tj = 25 C; see Figure 12 VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9 and 10 11 nC Static characteristics RDSon drain-source on-state resistance 3.2 3.8 m NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 2. Pinning information Table 2. Pin 1 2 3 4 mb S S S G D Pinning information Symbol Description source source source gate mounting base; connected to drain mbb076 Simplified outline mb Graphic symbol D G S 1234 SOT669 (LFPAK) 3. Ordering information Table 3. Ordering information Package Name PH3830L LFPAK Description plastic single-ended surface-mounted package (LFPAK); 4 leads Version SOT669 Type number 4. Limiting values Table 4. Symbol VDS VGS ID IDM Ptot Tstg Tj IS ISM EDS(AL)S Limiting values Parameter drain-source voltage gate-source voltage drain current peak drain current total power dissipation storage temperature junction temperature source current peak source current Tmb = 25 C tp 10 s; pulsed; Tmb = 25 C VGS = 10 V; Tmb = 100 C; see Figure 1 VGS = 10 V; Tmb = 25 C; see Figure 1 and 3 tp 10 s; pulsed; Tmb = 25 C; see Figure 3 Tmb = 25 C; see Figure 2 Conditions Tj 25 C; Tj 150 C Min -20 -55 -55 Max 30 20 62 98 290 62.5 150 150 52 150 250 Unit V V A A A W C C A A mJ In accordance with the Absolute Maximum Rating System (IEC 60134). Source-drain diode Avalanche ruggedness non-repetitive VGS = 10 V; Tj(init) = 25 C; ID = 70.7 A; Vsup 30 V; drain-source avalanche unclamped; tp = 0.1 ms energy PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 2 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 120 Ider (%) 80 03aa23 120 Pder (%) 80 03aa15 40 40 0 0 50 100 150 Tmb (C) 200 0 0 50 100 150 Tmb (C) 200 Fig 1. Normalized continuous drain current as a function of mounting base temperature Fig 2. Normalized total power dissipation as a function of mounting base temperature 003aaa377 103 ID (A) 102 Limit RDSon = VDS / ID tp = 10 s 10 DC 100 s 1 ms 10 ms 100 ms 1 10-1 10-1 1 10 VDS (V) 102 Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 3 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 5. Thermal characteristics Table 5. Symbol Rth(j-mb) Thermal characteristics Parameter Conditions Min Typ Max 2 Unit K/W thermal resistance from junction to mounting see Figure 4 base 10 Zth(j-mb) (K/W) 003aaa378 = 0.5 1 0.2 0.1 0.05 0.02 P = tp T single pulse tp t T 10-1 10-4 10-3 10-2 10-1 1 tp (s) 10 Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 4 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 6. Characteristics Table 6. Symbol V(BR)DSS VGS(th) Characteristics Parameter drain-source breakdown voltage gate-source threshold voltage Conditions ID = 250 A; VGS = 0 V; Tj = 25 C ID = 1 mA; VDS = VGS; Tj = 150 C; see Figure 8 ID = 1 mA; VDS = VGS; Tj = 25 C; see Figure 8 IDSS IGSS RDSon drain leakage current gate leakage current drain-source on-state resistance VDS = 30 V; VGS = 0 V; Tj = 25 C VGS = 15 V; VDS = 0 V; Tj = 25 C VGS = -15 V; VDS = 0 V; Tj = 25 C VGS = 10 V; ID = 25 A; Tj = 25 C; see Figure 9 and 10 VGS = 5 V; ID = 25 A; Tj = 25 C; see Figure 9 VGS = 10 V; ID = 25 A; Tj = 150 C; see Figure 9 and 10 Dynamic characteristics QG(tot) QGS QGD Ciss Coss Crss td(on) tr td(off) tf VSD trr total gate charge gate-source charge gate-drain charge input capacitance output capacitance reverse transfer capacitance turn-on delay time rise time turn-off delay time fall time source-drain voltage reverse recovery time VDS = 15 V; RL = 0.75 ; VGS = 4.5 V; RG(ext) = 4.7 ; Tj = 25 C; ID = 20 A VDS = 15 V; RL = 0.75 ; VGS = 4.5 V; RG(ext) = 4.7 ; Tj = 25 C; ID = 25 A VDS = 10 V; VGS = 0 V; f = 1 MHz; Tj = 25 C; see Figure 13 ID = 20 A; VDS = 10 V; VGS = 5 V; Tj = 25 C; see Figure 12 33 11 11 3190 1050 457 30 88 58 57 0.85 42 1.2 nC nC nC pF pF pF ns ns ns ns V ns Min 30 0.65 1 Typ 1.5 0.06 20 20 3.2 4 5.4 Max 2 1 100 100 3.8 4.9 6.5 Unit V V V A nA nA m m m Static characteristics Source-drain diode IS = 25 A; VGS = 0 V; Tj = 25 C; see Figure 11 IS = 20 A; dIS/dt = -100 A/s; VGS = 0 V; VDS = 25 V PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 5 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 60 ID (A) 40 10 5 3.5 003aaa379 50 ID (A) 40 003aaa380 VGS (V) = 3.1 3 30 2.9 2.8 20 Tj = 150 C 25 C 20 2.7 2.6 2.5 0 0 0.5 1 1.5 VDS (V) 2 10 0 1 2 3 VGS (V) 4 Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values 03aa36 Fig 6. Transfer characteristics: drain current as a function of gate-source voltage; typical values 2.5 03aa33 10-1 ID (A) 10-2 VGS(th) (V) 2 max 10-3 min 10-4 typ max 1.5 typ 1 min 10-5 0.5 10-6 0 1 2 VGS (V) 3 0 -60 0 60 120 Tj (C) 180 Fig 7. Sub-threshold drain current as a function of gate-source voltage Fig 8. Gate-source threshold voltage as a function of junction temperature PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 6 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 12 2.9 RDSon (m) 3 003aaa381 1.8 a 03al00 3.1 8 VGS (V) = 3.5 4 4 5 10 1.2 0.6 0 0 10 20 30 40 ID (A) 50 0 -60 0 60 120 Tj (C) 180 Fig 9. Drain-source on-state resistance as a function of drain current; typical values 50 003aaa383 Fig 10. Normalized drain-source on-state resistance factor as a function of junction temperature 10 VGS (V) 8 003aaa384 IS (A) 40 30 Tj = 150 C 20 25 C 6 4 10 2 0 0 0.2 0.4 0.6 0.8 VSD (V) 1 0 0 20 40 60 QG (nC) 80 Fig 11. Source current as a function of source-drain voltage; typical values Fig 12. Gate-source voltage as a function of gate charge; typical values PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 7 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 104 C (pF) 003aaa382 Ciss 103 Coss Crss 102 10-1 1 10 VDS (V) 102 Fig 13. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 8 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads SOT669 E b2 L1 A c2 A2 C E1 b3 mounting base D1 H D b4 L2 1 e 2 3 b 1/2 4 wM A c X e A A1 C (A 3) detail X L yC 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A A1 A2 A3 b b2 b3 2.2 2.0 b4 0.9 0.7 c c2 D (1) D1(1) E(1) E1(1) max 5.0 4.8 3.3 3.1 e 1.27 H 6.2 5.8 L 0.85 0.40 L1 1.3 0.8 L2 1.3 0.8 w 0.25 y 0.1 8 0 1.20 0.15 1.10 0.50 4.41 0.25 1.01 0.00 0.95 0.35 3.62 0.25 0.30 4.10 4.20 0.19 0.24 3.80 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT669 REFERENCES IEC JEDEC MO-235 JEITA EUROPEAN PROJECTION ISSUE DATE 04-10-13 06-03-16 Fig 14. Package outline SOT669 (LFPAK) PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 9 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 8. Revision history Table 7. Revision history Release date 20091117 Data sheet status Product data sheet Change notice Supersedes PH3830L-03 Document ID PH3830L_4 Modifications: * * The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Product data Product data Product data PH3830L-02 PH3830L-01 - PH3830L-03 PH3830L-02 PH3830L-01 20040302 20030918 20030502 PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 10 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 9. Legal information 9.1 Data sheet status Product status[3] Development Qualification Production Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification. Document status [1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 9.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 9.3 Disclaimers General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. 9.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. TrenchMOS -- is a trademark of NXP B.V. 10. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PH3830L_4 (c) NXP B.V. 2009. All rights reserved. Product data sheet Rev. 04 -- 17 November 2009 11 of 12 NXP Semiconductors PH3830L N-channel TrenchMOS logic level FET 11. Contents 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 9 9.1 9.2 9.3 9.4 10 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General description . . . . . . . . . . . . . . . . . . . . . .1 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .2 Thermal characteristics . . . . . . . . . . . . . . . . . . .4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . .10 Legal information. . . . . . . . . . . . . . . . . . . . . . . . 11 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 11 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Contact information. . . . . . . . . . . . . . . . . . . . . . 11 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 17 November 2009 Document identifier: PH3830L_4 |
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